1. Field of the Invention
The present invention relates to a serial type interface circuit for decreasing the power consumption of an interface circuit and a device when data is transferred between a host and the device via a high-speed serial interface, a power saving method thereof, and a device having such a serial interface.
2. Description of the Related Art
As the processing of microprocessors (MPU) improves, the improvement of the transfer speed between the host computer and a peripheral device (e.g. hard disk drive) is demanded. As such demand increases, a high-speed serial interface using a packet type protocol has been proposed.
The parallel interface transfers data in parallel via a plurality of data lines, so data on the plurality of signal lines must be synchronized, and interference and noise between the signal lines becomes a problem, which makes it difficult to increase the transfer speed.
A serial interface, on the other hand, transfers the data in serial via a single data line, so there is only a pair of signal lines, a timing shift does not occur, and stable high-speed transfer is possible. SATA (Serial AT Attachment), for example, is attracting attention as a serial interface which is a low voltage type, and has a several giga bps transfer speed.
FIG. 8 is a block diagram of a serial ATA system. The host 2 and the peripheral device 1 (hard disk drive in this case) are connected by the SATA interface 3.
The host 2 operates a plurality of application programs 21 based on the control of the operating system 20. The driver 22 drives the peripheral device 1 based on the control of the operating system 20. In this driver 22, the SATA host bus adapter 23 is disposed for the SATA interface 3.
The SATA host bus adapter 23 comprises a transport layer 24 for performing transfer control, a link layer 25 for performing frame transmission and reception control, and a physical layer 26 for performing physical control of the interface.
In the peripheral device 1, the SATA device 10 is disposed in the device (hard disk drive) 11 for SATA interface connection.
The SATA device 10 comprises a physical layer 12 for performing physical control of the interface, a link layer 13 for performing frame transmission/reception control, a transport layer 14 for performing transfer control, an application layer 15 for controlling the device, and a firmware 16 for controlling the transport layer 14 and the application layer 15 according to the status of the device 11.
For a system having such an interface, decreasing power consumption is demanded and a power save mode, to decrease power consumption when the peripheral device 1 is not used, is provided.
For example, if the host 2 recognizes that the peripheral device 1 is not used for a predetermined time, the host 2 issues the power save command to the device 1 so as to shift the device 1 to the power save mode, or the device 1 itself monitors commands and data from the host 2 and shifts to the power save mode when a command is not received from the host 2 for a predetermined time (e.g. refer to “Serial ATA: High-speed Serialized AT Attachment”, Serial ATA Workshop Revision 1.0a, Jan. 7, 2003 issue).
By providing such a power save mode in the device 1, the power consumption of the device 1 can be decreased, and in particular, the power save mode is appropriate to apply to a device which requires low power consumption because of power capacity restrictions, such as a notebook personal computer and a portable terminal.
FIG. 9 is a diagram depicting the power save mode of a conventional interface, and FIG. 10 and FIG. 11 are diagrams depicting the power save mode inside a conventional device.
As FIG. 9 shows, the interface of the above mentioned SATA device 10 comprises a physical layer 12 and a link layer 13. The physical layer 12 further comprises an analog circuit 12-1 including an analog interface circuit, a timing recovery circuit, and a synchronization PLL circuit, and a digital circuit 12-2 which performs S-P (Serial-Parallel) conversion, P-S (Parallel-Serial) conversion, data extraction, and synchronization control. The digital circuit 12-2 operates with the clock of the analog circuit 12-1.
The link layer 13 has a link digital circuit for performing link establishment, frame reception, transfer, encoding, CRC check and frame flow control. The link digital circuit 13 operates with the clock of the digital PLL 18 of the SATA device 10.
In such an interface, conventionally the focus was to decrease the current of the analog portion 12-1 which consumes relatively high power, while the power consumption of the digital portion was not intentionally controlled.
In the power save mode inside the device 10, on the other hand, internal digital clock operation is stopped and returned. This control is completely performed by firmware 16 of the CPU. The firmware during a power save takes enormous time if complicated control is involved, since the CPU performance is restricted during the power save.
In other words, as FIG. 10 and FIG. 11 show, in the SATA device 10, the firmware 16 must perform complicated procedures to confirm the hardware status to prevent an unexpected stoppage of the clock during frame reception. This is the same for returning.
For example, in the case of the power save mode entering processing, it is checked whether frames from host 2 are being received, whether frame stop processing was success, and whether a frame request was received, as shown in FIG. 11, then the frame stop processing, clock stop processing and other stop processings are performed, and power save mode processing is completed.
In the return processing from the power save mode, as shown in FIG. 10, return processing such as initialization is performed, then clock return processing is performed, frame restart processing is subsequently performed, and then return processing is completed.
In the power save mode of a conventional interface, the return time of the analog circuit 12-1 tends to increase as the miniaturization of semiconductor technology advances. To improve performance, however, it is necessary that the return time is short, and if parts which power is cut are increased, then it is difficult to keep to the return time standard (e.g. two types in the case of Serial ATA, Slumber=10 ms, Partial=10 μs), so the parts to cut power are restricted. This makes it difficult to sufficiently suppress power consumption.
Also as the digital portion 12-2 becomes complicated and there is a relative increase in power consumption, this increase in power consumption can no longer be ignored. If the clock of the digital portion is stopped, however, the above mentioned return time standard cannot be kept, which makes to difficult to implement power saving of the digital portion.
Also in the case of the internal power saving of a conventional device, frame type protocol is normally used for the serial type interface, but an unexpected clock stoppage during frame reception is avoided, and as mentioned above, the firmware 16 requires a complicated procedure to confirm the hardware status, which takes enormous time. This is the same for the returning.
The time required for entering and returning from power saving mode influences the performance of the entire system, so decreasing this entering and return time requires dropping power consumption without dropping performance. If the return time is decreased, it difficult to suppress power consumption as much as desired, and performance decreases in power save mode. Therefore conventional devices are not appropriate for an application where a further decrease in power consumption is critical, and where performance is also demanded (e.g. mobile equipment).